1. Field of the Invention
The present invention relates to a semiconductor memory device having a memory cell with a read bit line connected to a data output node thereof and also with a write bit line connected to a data input node thereof and enabling operations for reading and writing data via the pair of bit lines.
2. Description of the Related Art
There has been known the so-called gain cell as a memory cell with the data input node connected to a write bit line and the data output node connected to a read bit line.
In the gain cell, there is provided an amplifier transistor that stores an electric charge in the so-called capacitive component added to a gate for data storage, and the data stored in the memory cell is read out by checking a voltage change in the read bit line in response to whether the amplifier transistor is turned ON or not when reading out the data.
FIG. 1 illustrates an equalizing circuit constituting a three-transistor type gain cell (hereinafter simply referred to as a memory cell).
The memory cell MCa shown in FIG. 1 includes one write transistor WT and two read transistors, namely a select transistor ST and an amplifier transistor AT.
Either source or drain region of the write transistor WT is connected to a write bit line WBL, the other region is connected to a storage node SN, and a gate is connected to a write word line WWL.
A source of the amplifier transistor AT is connected to the ground level voltage (a common source line CSL), a drain is connected to a source of the select transistor ST, and a gate is connected to a storage node SN.
A drain of the select transistor ST is connected to a read bit line RBL, and a gate is connected to a read word line RWL.
FIG. 2 illustrates an example of a memory cell control circuit.
As shown in FIG. 2, a plurality of the memory cell MCa each having the configuration, as shown in FIG. 1, is arrayed along the column direction. The memory cells MCa share the read bit line RBL and the write bit line WBL, namely a bit line pair.
Connected to the bit line pair is a precharge circuit 50 including two precharge transistors including two precharge transistors PTr and PTw each including a PMOS transistor. The precharge transistor PTr has a source and a drain, one of which is connected to the read bit line RBL and the other is connected to a voltage supply line of a voltage VRBL. The precharge transistor PTw has a source and a drain, one of which is connected to the write bit line WBL and the other is connected to a voltage supply line of a VWBL. The two precharge transistors PTr and PTw are controlled commonly by a precharge enable signal PRE.
A cross-coupled latch type sense amplifier (hereinafter referred to as sense amplifier) SA is connected to the read bit line RBL and the write bit line WBL.
In the sense amplifier SA, as illustrated in FIG. 2, an input terminal and an output terminal of the inverter including a PMOS transistor 21 and a NMOS transistor 22 respectively are cross-connected.
Between a shared source for the two of the transistors 21 and the voltage line, a PMOS transistor 23 controlled by a low-active SA enable inversion signal (or SAEP) is connected. Between a shared source for the two of the NMOS transistors 22 and the grounded connection, an NMOS transistor 24 controlled by a high-active SA enable signal (or /SAEN) is connected. The two AS enable signals (SAEN and /SAEP) are shared by other sense amplifiers arrayed in a direction of rows (not shown).
The memory cell control circuit using the cross-coupled latch type sense amplifier SA is described, for instance, in Japanese Patent Laid-Open NO. 2001-291389 (hereinafter referred to as Patent document 1).
A BL selector 6B is provided as a circuit for electrically disconnecting the read bit line RBL and write bit line WBL that connect to the precharge circuit 50 and the sense amplifier SA from other control circuits.
The BL selector 6B includes an NMOS switch 61r connected to both of the read bit lines RBL and a global read bit line GRBL, and an NMOS switch 61w connected to both of the write bit lines WBL and a global write bit line GWBL.
FIGS. 3A to 3G are timing charts for illustrating an operation for reading “L” data read from the storage node SN. As shown in FIG. 3C, the write word line WWL is always kept in the inactive state (at “L” level) during the read operation.
During an interval to the time point T0 shown in FIG. 3A, because the low-active precharge enable signal PRE is at the “L” level, both of the precharge transistors PTr and PTw are in the ON state. Thus, the voltage VRBL (voltage Vdd=1.8 V, for example) is precharged in the read bit line RBL, while a voltage VWBL (1.4 V, for example) which is lower than the voltage VRBL is precharged. At the time point T0, the precharge enable signal PRE is set in the inactive state (to the “H” level), and thus the bit lines RBL and WBL operate in the floating state while the precharged voltage is maintained.
As shown in FIG. 3B, at the time point T1, an “H” level pulse, for instance, the power supply voltage Vdd is applied to the read word line RWL. Thus, though the select transistor ST can be turned ON, the amplifier transistor AT is maintained in the OFF state because the voltage of the storage node SN is at the “L” level. Therefore, the voltage of the read bit line RBL is kept at the power supply voltage Vdd (1.8 V).
As shown in FIGS. 3D and 3E, at the time point T2, the SA enable signal SAEN is activated to the “H” level and the SA enable inversion signal SAEP is activated to the “L” level. With the operation, the cross-coupled latch type sense amplifier SA operates and amplifies a fine potential difference (about 0.4 V) between a voltage in the read bit line RBL and that in the write bit line WBL to a signal at the voltage 1.8 V. The signal generated when the voltage of the read bit line RBL is higher than the voltage of the write bit line WBL corresponds to an “L” data stored in the memory cell MCa.
Then, the Y switch signal YSW shown in FIG. 3F is set to the “H” level for activating the NMOS switch pair 61r and 61w constituting the BL selector 6B shown in FIG. 2 the ON state, and the read-out “L” data is transferred to a successive circuit.
FIG. 4A to FIG. 4G are timing charts each illustrating an operation for reading “H” data from the storage node SN.
The voltage level control for the operation (shown in FIG. 4A to FIG. 4F) is the same as that in the “L” data read operation described above, except that the data stored in the storage node SN is at the “H” level.
During the “H” data read operation, the data stored in the storage node SN is set at a higher voltage than a threshold voltage that enables the amplifier transistor AT shown in FIG. 1 to be activated into the ON state, and the voltage is maintained during the read operation.
Therefore, at the time point T1 shown in FIG. 4B, the read word line RWL is activated causing the select transistor ST to be activated into the ON state, and a voltage is applied to a section between the amplifier transistor AT source and the drain, and thus the transistor AT is activated into an ON state. Therefore, the voltage of the read bit line RBL is discharged, via the select transistor ST and the amplifier transistor AT, to a common source line CSL. Then, as shown in FIG. 4G, a voltage inversion is generated, enabling the voltage of the read bit line RBL which is lower than the voltage of the write bit line WBL.
As shown in FIG. 4D and FIG. 4E, when the sense amplifier is activated at the time point T2, the sense amplifier SA amplifies the potential difference between the read bit line RBL and the write bit line WBL after occurrence of the voltage inversion described above into the signal having the voltage of 1.8 V. The signal generated when the voltage of the read bit line RBL is lower than the voltage of the write bit line WBL corresponding to the “H” data stored in the memory cell MCa.
Then the Y switch signal YSW is set at the “H” level, as shown in FIG. 4F, with the BL selector 6B shown in FIG. 2 activated, and the read “H” data is transferred to a successive circuit.
FIG. 5A to FIG. 5I are timing charts for illustrating an operation for writing the “L” data to the storage node SN. FIG. 6A to FIG. 6I are timing charts for illustrating an operation for writing the “H” data to the storage node SN.
In both of the operations shown in FIG. 5 and FIG. 6, it is necessary to set a voltage enabling the read operation and the refresh operation to the write bit line WBL, before the activation of the word line WWL (or before to time T4). The reasons are described below.
FIG. 2 is a view illustrating a configuration including an array of memory cells and a control circuit (hereinafter referred to as a column unit). It is to be noted that, in an actual semiconductor memory device, a plurality of the same configurations is repetitively arranged along the row direction. The memory cells in each line share the write word line WWL and the read word line RWL.
An operation for writing data by the prespecified number of bits, for instance, by 1 byte (8 bits) is necessary in each line to enable a random access by the device. For the purpose, write data is set from a write circuit not shown in the global write bit line GWBL in the column unit as a target for the write operation and the Y switch signal YSW is activated to forcefully update a potential in the write bit line WBL with the write data. In a column unit not selected as a target for the write operation, a refresh operation is performed. Specifically, after the read operation for reading the data stored in the memory cell to the read bit line RBL is performed, logic of the cell store data are inverted from that of the read data (Refer to FIG. 3G and FIG. 4G). By the read operation, the cell-stored data having a maximum voltage (=1.8 V) is set in the write bit line WBL (Refer to FIG. 3G and FIG. 4G). The column unit is controlled so that the Y switch signal YSW does not activate. Thus, the refresh operation is enabled by the successive activation of the word line WWL.
As described above, in the semiconductor memory in the past providing controls as described above, it is necessary to set a voltage enabling an operation for rewriting data in the write bit line WBL by performing a data read operation before a data write operation.
Until the time point T3 shown in FIG. 5 and FIG. 6, the read operation as described by referring FIG. 3 and FIG. 4 is performed, and description of the operation is omitted herein.
However, voltage of write data in the operation for writing “L” data (FIG. 5) is inverted from that in the operation for writing “H” data (FIG. 6), and, therefore, a voltage in the global read bit line GRBL (in FIG. 5) is inverted from that in the global write bit line GWBL (in FIG. 6).
More specifically, when writing “L” data, as shown in FIG. 5H, a voltage at a high level (1.8 V) is set in the global read bit line GRBL, and a voltage at a low level (0 V) is set in the global write bit line GWBL.
In contrast, when writing “H” data, a voltage at a low level (0 V) is set in the global read bit line GRBL, as shown in FIG. 6H, and a voltage at a high level (1.8 V) is set in the global write bite line GWBL.
After completion of the read operation, the Y switch signal YSW shown in FIG. 2 is activated. Then, voltages in the bit line pair (read bit line RBL and the write bit line WBL) are inverted in both column units including a cell as a target for “L” data write and other column units including a cell as a target for “H” data write in FIG. 5 and FIG. 6, respectively. To describe the operation from a contrary point of view, a voltage (a write voltage) in the global write bit line GWBL or the like is set so that the inversion occurs for the target cell for data write operation.
On the other hand, in a column unit including a cell not selected as a target for the data write operation and not shown in FIG. 5, the Y switch signal YSW does not shift to the “H” level, the bit line pair preserved the state just before the time point T3 even after the time point T3.
Next, as shown in FIG. 5C and FIG. 6C, the write word line WWL is set to a high level at the time point T4. With this operation, the write transistor WT shown in FIG. 1 is turned ON, and write data forcefully set in the write bit line WBL is written in the storage node SN.
As described above, in the column unit not selected according to the Y switch signal YSW, the storage node voltage previously written therein is amplified and the data is read into the write bit line WBL. Therefore, when the write word line WWL is activated, the data read out, as described above, is again written in the storage node SN of the not-selected memory cell, thus a refresh operation is carried out.
After the data write operation is performed, a voltage in the write word line WWL is dropped to a low level (0 V) as shown in FIG. 7, and the write transistor WT is turned OFF. In this step, a voltage in the read word line RWL is kept at 0 V, and the OFF state of the select transistor ST is maintained until a data read operation is performed next. In this standby state, the storage node SN floats, and the accumulated charge is preserved.
The accumulated charge is accumulated mainly in a capacitance between a source side dispersion layer of the transistor WT and a substrate, in a capacitance between the source side dispersion layer and a gate of the write transistor WT, and in a MOS gate capacitance (including parasitic capacitance) of the amplifier transistor AT. Therefore, a voltage in the storage node SN attenuates due to a dispersion layer junction leak in the write transistor WT, a gate leak in the amplifier transistor AT and the like. To prevent the attenuation, it is necessary to perform data rewrite (refreshing) each time a prespecified period of time passes after completion of the write operation. In the configuration as described above, the refreshing operation can be carried out when writing data any other memory cell connected to the same row.